[AKD4440-A] 2009/5 - 1 - general description the AKD4440-A is an evaluation board for the ak4440, 24bit dac with 2vrms line output for cost and performance based audio systems. the AKD4440-A has the interface with akm?s a/d converter evaluation boards and the inte rface with digital audio systems via optic al connector. theref ore, it is easy to evaluate the ak4440. ? ordering guide AKD4440-A --- ak4440 evaluation board function ? compatible with 2 types of input data interface - direct interface with akm?s a/d con verter evaluation boards via 10-pin header - on-board ak4118 as dir, which accepts optical or bnc inputs ? optical output for internal dit ? bnc connector for an external clock input ? bnc connector for dac output ak4118 (dir) 10 pin header dsp data 74lvc541 digital in bnc ak4440 dgnd vcc vdd avss1 lout1 rout1 analog out lout2 rout2 lout3 rout3 lout4 rout4 avdd avss2 figure 1 . AKD4440-A block diagram . ak4440 evaluation board rev.3 AKD4440-A
[AKD4440-A] 2009/5 - 2 - ? operation sequence 1) set up the power supply lines. [vdd] (red) = 4.5 5.5v (typ. 5.0v, for ak4440) [vcc] (red) = 2.7 3.6v (typ. 3.3v, for ak4118, for 74lvc541 and for logic) [avdd] (red) = 4.5 5.5v (typ. 5.0v, ak4440) [avss1] (black) = 0v [avss2] (black) = 0v [dgnd] (black) = 0v each supply line should be distributed from the power supply unit. 2) set-up the evaluation modes, jumper pins and dip switches (see the followings.) 3) power on. when ak4118 is used, the ak4118 should be reset once by bringing sw2 ?l? upon power-up. ? evaluation mode 1) d/a part evaluation using optical or s/pdif input use port1 (rx3: opt) or j2 (rx3: bnc). the ak4118 (dir) generates mclk, bick, lrck and sdti from the received data through optical connector (torx141) or bnc connector. this evaluation mode should be used for the evaluation using cd test disk. nothing should be connected to port3 (dsp). the sel ection of opt and bnc should be done by jp8 (rx1) jp7 lrck jp4 mclk dir ext dir ext jp5 bick dir ext jp6 sdti1 jp8 rx1 opt bnc 2) d/a part evaluation using 10-pin c onnector on the akm?s a/d evaluation board use port3 (dsp). it is able to evaluate the ak4440, connecting the 10-pin connector on the akm?s a/d evaluation board and port3 (dsp) via 10-line flat cable. mclk, bick, lrck and sdti are sent from the a/d converter evaluation board to the akd4440 through port3 (dsp) via 10-line flat cable. jp7 lrck jp4 mclk dir ext dir ext jp5 bick dir ext jp6 sdti1 3) d/a part evaluation using port3 (dsp), and supplyi ng all interface signals from external equipments in case of using port3 (dsp), and supplying signal s (mclk, bick, lrck, sdti) that is needed for the ak4440 from external equipments, set up as following. jp7 lrck jp4 mclk dir ext dir ext jp5 bick dir ext jp6 sdti1
[AKD4440-A] 2009/5 - 3 - ? other jumper pins set up (1) jp1 (sdti1): select the input of sdti2 pin open: separated short: (2) jp2 (sdti1): select the input of sdti3 pin open: separated short: (3) jp3 (sdti1): select the input of sdti4 pin open: separated short: (4) jp14 (vdd): vdd and vcc open: separated short: prohibition (5) jp15 (vdd): vdd and avdd open: separated short: prohibition (6) jp16 (gnd): analog ground and digital ground open: separated short: prohibition
[AKD4440-A] 2009/5 - - 4 - - ? dip switch set up [s1]: ak4118 setting no. pin l h default 1 dif1 l 2 dif0 setting of ak4118 audio interface format (refer table 2.) l 3 ocks1 h 4 ocks0 selection of ak4118 master clock output frequency (refer table 3.) l table 1. set up modes of ak4118 mode dif1 dif0 sdto 4 l l 24bit, left justified (default) 5 l h 24bit, i 2 s table 2. audio data format of ak4118 ocks1 ocks0 mcko1 fs (max) l l 256fs 96khz h l 512fs 48khz (default) h h 128fs 192khz table 3. mclk frequency of ak4118 [sw2]: ak4440 setting no . pin off (l) on (h) default 1 smute soft mute pin in parallel mode : ?disable? soft mute pin in parallel mode : ?enable? off 2 acks normal speed mode (parallel control mode) auto setting mode (parallel control mode) off 3 dif0 24-bit msb (parallel control mode) 24-bit i 2 s (parallel control mode) off 4 tdm0b tdm256 mode (parallel control mode) normal mode (parallel control mode) on 5 dem0 de-emphasis filter enable pin in parallel mode. this pin is valid in parallel mode. (refer table 5 .) on 6 dem1/i2 s de-emphasis filter enable pin in parallel mode. this pin is valid in parallel mode. (refer table 5 .) off 7 p/s serial control mode parallel control mode off table 4. sw2 set-up dem1 pin dem0 pin mode 0 0 44.1khz 0 1 off (default) 1 0 48khz 1 1 32khz table 5. de-emphasis filter control (normal speed mode) ? toggle switch [sw2] ak4118-pdn: switch for power down reset of ak4118.keep ?h? during operation of ak4118. power down reset of ak4118 will be done by setting sw2 to ?l? once, after power on.
[AKD4440-A] 2009/5 - - 5 - - ? register control akd4440 can be controlled via the printer port (para llel port) of ibm-at compatible pc. connect port3 (up-i/f) to pc by 10-line flat cable packed with this. take care of the direction of connector. there is a mark at connector. connect the mark of 10-pin conn ector to pin1 of port3. (figure 2.) connect cdto/sda(ack) cclk/scl cdti/sda 10pin header 10pin connector 10 wire flat cable pc AKD4440-A 2 10 9 port3 up-i/f red csn figure 2. port3 pin layout ? analog output circuit the dac of ak4440 outputs analog audio signals through j3 and j4. c19 3.3n + c18 (short) c21 3.3n r19 (short) + c20 (short) r15 560 j3 bnc-r-pc 1 2 3 4 5 r18 560 j4 bnc-r-pc 1 2 3 4 5 rout1 lout1 r17 (open) r20 (open) ak4440-rout1 ak4440-lout1 r16 (short) figure 3. lout/rout output circuit * akm assumes no responsibility for the troubl e when using the above circuit examples.
[AKD4440-A] 2009/5 - - 6 - - control soft manual evaluation board and control soft settings 1. set an evaluation board properly. 2. connect the evaluation board to an ibm pc/at compatible pc by a 10wire flat cable. be aware of the direction of the 10pin header. when running this control soft on the windows 2000/xp, the driver which is included in the cd must be installed. refer to the ?dri ver control install manual for akm devi ce control software? for installing the driver. when running this control soft on the windows 95/98/me, driver installing is not necessary. this control soft does not support the windows nt. 3. proceed evaluation by follo wing the process below. operation screen 1. start up the control program following the process above. the operation screen is shown below.
[AKD4440-A] 2009/5 - - 7 - - operation overview function, register map and testing tool can be controlled by th is control soft. these controls are selected by upper tabs. buttons which are frequently used such as register initializing button ?write default?, are located outside of the switching tab window. refer to the ? dialog boxes? for details of each dialog box setting. 1. [port reset]: for when connecting to usb i/f board (akdusbif-a) click this button after the control soft starts up when connecting usb i/f board (akdusbif-a). 2. [write default]: register initializing when the device is reset by a hardware reset, use this button to initialize the registers. 3. [all write]: executing write commands for all registers displayed. 4. [save]: saving current register settings to a file. 5. [load]: executing data write from a saved file. 6. [all req write]: ?all req write? dialog box is popped up. 7. [data r/w]: ?data r/w? dialog box is popped up. 8. [read]: reading current register settings and display on to the register area (on the right of the main window). this is different from [all read] button, it does not reflect to a register map, only displaying hexadecimal.
[AKD4440-A] 2009/5 - - 8 - - tab functions 1. [reg]: register map this tab is for a register writing and reading. each bit on the register map is a push-button switch. button down indicates ?h? or ?1? and the bit name is in red (when read only it is in deep red). button up indicates ?l? or ?0? and the bit name is in blue (when read only it is in gray) grayout registers are read only registers. they can not be controlled. the registers which is not defined in the datasheet are indicated as ?---?.
[AKD4440-A] 2009/5 - - 9 - - [write]: data writing dialog it is for when changing two or more bits on the same address at the same time. click [write] button located on the right of th e each corresponded address for a pop-up dialog box. when checking the checkbox, the register will be ?h? or ?1?, when not checki ng the register will be ?l? or ?0?. click [ok] to write setting value to the registers, or click [cancel] to cancel this setting. [read]: data read click [read] button located on the right of the each corresponded address to execu te register reading. after register reading, the display will be updated regarding to th e register status. button down indicates ?h? or ?1? and the bit name is in red (when read only it is in deep red). button up indicates ?l? or ?0? and the bit name is in blue (when read only it is in gray) please be aware that button statuses will be changed by read command.
[AKD4440-A] 2009/5 - - 10 - - dialog boxes 1. [all req write]: all req write dialog box click [all reg write] button in the main window to open register setting files. register setting files saved by [save] button can be applied. [open (left)]: selecting a register setting file (*.akr). [write]: executing register writing. [write all]: executing all register writings. writings are executed in descending order. [help]: help window is popped up. [save]: saving the register setting file a ssignment. the file name is ?*.mar?. [open (right)]: opening a saved register setting file assignment ?*. mar?. [close]: closing the dialog box and finish the process. *operating suggestions (1) those files saved by [save] button and opened by [o pen] button on the right of the dialog ?*.mar? should be stored in the same folder. (2) when register settings are changed by [save] button in the main window, re-read the file to reflect new register settings.
[AKD4440-A] 2009/5 - - 11 - - 2. [data r/w]: data r/w dialog box click the [data r/w] button in the main window for data read/write dialog box. data write is available to specified address. address box: input data address in hexadecimal numbers for data writing. data box: input data in hexadecimal numbers. mask box: input mask data in hexadecimal numbers. this is ?and? processed input data. [write]: writing to the address specified by ?address? box. [read]: reading from the address specified by ?address? box. the result will be shown in the read data box in hexadecimal numbers. [close]: closing the dialog box and finish the process. data writing can be cancelled by this button instead of [write] button. *the register map will be updated afte r executing [write] or [read] commands.
[AKD4440-A] 2009/5 - - 12 - - measurement results [measurement condition] ? measurement unit : audio preci sion system two cascade (ap2) ? mclk : 512fs ? bick : 64fs ? fs : 44.1khz ? bit : 24bit ? power supply : vdd=avdd=5v ? interface : dir ? temperature : room table data dac1 on parameter input signal filter condition lch rch s/(n+d) 1khz, 0db 20klpf 92.8 92.8 dr 1khz, -60db 20klpf, a-weighted 105.0 105.0 s/n ?0? data 20klpf, a-weighted 105.0 105.0
[AKD4440-A] 2009/5 - - 13 - - plot data akm fft 0db fs=44.1khz,fin=1khz -180 +0 -160 -140 -120 -100 -80 -60 -40 -20 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 4. fft (0db) akm fft -60db fs=44.1khz,fin=1khz -180 +0 -160 -140 -120 -100 -80 -60 -40 -20 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 5. fft (-60db)
[AKD4440-A] 2009/5 - - 14 - - akm fft no signal fs=44.1khz,fin=1khz -180 +0 -160 -140 -120 -100 -80 -60 -40 -20 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 6. fft (no signal) akm fft out of band noise fs=44.1khz,fin=1khz -180 +0 -160 -140 -120 -100 -80 -60 -40 -20 d b r a 20 100k 50 100 200 500 1k 2k 5k 10k 20k 50k hz figure 7. fft (out of band noise)
[AKD4440-A] 2009/5 - - 15 - - akm thd + n vs. input level fs=44.1khz,fin=1khz -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a -120 +0 -100 -80 -60 -40 -20 dbfs figure 8. thd + n vs. input level akm thd + n vs. input frequency fs=44.1khz,0db -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 9. thd + n vs. input frequency
[AKD4440-A] 2009/5 - 16 - akm frequency response fs=44.1khz,0db -1 +1 -0.8 -0.6 -0.4 -0.2 +0 +0.2 +0.4 +0.6 +0.8 d b r a 2k 20k 4k 6k 8k 10k 12k 14k 16k 18k hz figure 10. frequency response akm crosstalk fs=44.1khz,0db -120 +0 -100 -80 -60 -40 -20 d b 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 11. crosstalk
[AKD4440-A] 2009/5 - 17 - akm linearity fs=44.1khz,fin=1khz -140 +0 -120 -100 -80 -60 -40 -20 d b r a -140 +0 -120 -100 -80 -60 -40 -20 dbfs figure 12. linearity
[AKD4440-A] 2009/5 - 18 - revision history date (yy/mm/dd) manual revision board revision reason page contents 08/11/13 km097200 0 first edition 5 ak4118 setting change: table 3. audio data format of ak4118=> table 2. audio data format of ak4118, (24bit, i 2 s=>24bit, left justified) selection of ak4114 master clock output frequency (refer table 4.) => selection of ak4118 master clock output frequency (refer table 3.) 08/12/01 km097201 0 correction 16 addition of circuit chart around ak4440 08/12/03 km097201 0 correction 6 change in control soft manual 09/01/13 km097202 1 correction 5 change in analog output 1 board revision: rev.1 rev.2 09/04/07 km097203 2 correction 12~17 device revision change: rev.a ? rev.b the addition of table data and plot data 6,8 change in control soft manual 09/05/08 km097204 3 correction 22 circuit change port3 important notice z these products and their specifications ar e subject to change without notice. when you consider any use or application of these products, please make inquiries th e sales office of asahi kasei microdevices corporation (akm) or authorized distributor s as to current status of the products. z akm assumes no liability for infringement of any patent, intellectua l property, or other rights in the application or use of an y information contained herein. z any export of these products, or devices or systems containing th em, may require an export license or other official approval u nder the law and regulations of the country of export pertaining to customs and tariffs, currency exch ange, or strategic materials. z akm products are neither intended nor aut horized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by representative di rector of akm. as used here: note1) a critical component is one whose failu re to function or perform may reasona bly be expected to result, whether directly or indirectly, in the loss of the safety or effectiven ess of the device or system cont aining it, and which must theref ore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or in tended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fi elds, in which its failure to function or perform may reasonabl y be expected to result in loss of life or in signi ficant injury or damage to person or property. z it is the responsibility of the buyer or di stributor of akm products, who distributes, disposes of, or othe rwise places the pro duct with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agr ees to assume any and all responsibility and liability for and hold akm ha rmless from any and all claims arising from the use of said product in the absence of such notification.
a a b b c c d d e e e e d d c c b b a a ak4440-mclk ak4440-bick ak4440-sdti1 ak4440-lrck ak4440-smute/cns/cad0 ak4440-acks/cclk/scl ak4440-dif0/cdti/sda ak4440-sdti1 ak4440-sdti1 ak4440-sdti1 ak4440-tdm0b ak4440-i2c/dem1 ak4440-p/s avdd ak4440-rout1 vdd ak4440-dem0 ak4440-lout1 ak4440-lout2 ak4440-rout2 ak4440-lout3 ak4440-rout3 ak4440-lout4 ak4440-rout4 title size document number rev date: sheet of ak4440 7 akd4440 a3 15 friday, may 08, 2009 title size document number rev date: sheet of ak4440 7 akd4440 a3 15 friday, may 08, 2009 title size document number rev date: sheet of ak4440 7 akd4440 a3 15 friday, may 08, 2009 mclk tdm0b lout4 dem0 lout3 lout1 rout1 rout2 lout2 rout3 i2c rout4 smute/cns/cad0 acks/cclk/scl dif0/cdti/sda p/s vdd bick sdti1 lrck avdd tp3 sdti1 tp3 sdti1 1 tp17 avdd tp17 avdd 1 tp6 lout1 tp6 lout1 1 tp14 rout3 tp14 rout3 1 u1 ak4440 u1 ak4440 mclk 1 bick 2 sdti1 3 lrck 4 test 5 smute/csn/cad0 6 acks/cclk/scl 7 dif0/cdti/sda 8 sdti2 9 sdti3 10 sdti4 11 tdm0b 12 dem0 13 i2c/dem1 14 p/s 15 vdd 30 vss2 29 cp 28 cn 27 vee 26 lout1 25 rout1 24 lout2 23 rout2 22 lout3 21 rout3 20 lout4 19 rout4 18 vss1 17 avdd 16 tp16 rout4 tp16 rout4 1 c5 0.1uf c5 0.1uf tp9 sdti2 tp9 sdti2 1 + c6 10uf + c6 10uf 1 2 + c2 10uf + c2 10uf 1 2 tp12 lout3 tp12 lout3 1 jp3 (2x1) jp3 (2x1) tp15 lout4 tp15 lout4 1 c1 0.1uf c1 0.1uf cn2 30pin_2 cn2 30pin_2 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 tp11 sdti3 tp11 sdti3 1 tp10 rout2 tp10 rout2 1 tp1 mclk tp1 mclk 1 tp5 bick tp5 bick 1 + c4 1uf + c4 1uf 1 2 jp1 (2x1) jp1 (2x1) tp8 lout2 tp8 lout2 1 cn1 30pin_4 cn1 30pin_4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tp13 sdti4 tp13 sdti4 1 tp7 rout1 tp7 rout1 1 tp4 lrck tp4 lrck 1 jp2 (2x1) jp2 (2x1) tp2 vdd tp2 vdd 1 + c3 1uf + c3 1uf 1 2
a a b b c c d d e e e e d d c c b b a a dif0 vcc dif1 ocks0 ocks1 dif0 ocks0 ocks1 4118-vcc ak4118-rx3 4118-vcc vcc1 vcc 4118-vcc dif1 ak4440-mclk ak4440-bick ak4440-lrck ak4440-sdti1 ext-lrck ext-mclk ext-bick vcc vcc ak4118-rx3 vcc vcc title size document number rev date: sheet of dir&clock 7 akd4440 a3 25 friday, may 08, 2009 title size document number rev date: sheet of dir&clock 7 akd4440 a3 25 friday, may 08, 2009 title size document number rev date: sheet of dir&clock 7 akd4440 a3 25 friday, may 08, 2009 ak4118-pdn hl dif0 dif1 ocks0 ocks1 ak4118-int0 ak4118-int1 dir mclk ext ext lrck sdti1 bick ext dir dir h l rx3(opt) rx3(bnc) opt bnc rx1 dsp mclk bick sdti1 lrck sdti2 sw1 ate1d-2m3 sw1 ate1d-2m3 2 1 3 r13 75 r13 75 rp1 47k rp1 47k 4 3 2 1 r5 51 r5 51 jp6(2x1) jp6(2x1) jp4(3x1) jp4(3x1) + c14 10u + c14 10u c16 0.1u c16 0.1u u4c 74hc14 u4c 74hc14 5 6 r8 10k r8 10k u3 74lvc541a u3 74lvc541a a1 2 a2 3 a3 4 a4 5 a5 6 a6 7 a7 8 a8 9 g1 1 g2 19 y1 18 y2 17 y3 16 y4 15 y5 14 y6 13 y7 12 y8 11 vcc 20 gnd 10 + c8 10u + c8 10u r6 51 r6 51 r3 (open) r3 (open) s1 sw dip-4 s1 sw dip-4 1 2 3 4 8 7 6 5 jp5(3x1) jp5(3x1) u4d 74hc14 u4d 74hc14 9 8 jp8 (3x1) jp8 (3x1) c13 0.1u c13 0.1u l1 47u l1 47u 1 2 r7 51 r7 51 + c7 10u + c7 10u u4e 74hc14 u4e 74hc14 11 10 r1 51 r1 51 r11 (open) r11 (open) jp7 (3x1) jp7 (3x1) + c15 10u + c15 10u c9 0.1u c9 0.1u c11 0.1u c11 0.1u u4f 74hc14 u4f 74hc14 13 12 7 14 r10 10k r10 10k j1 bnc-r-pc j1 bnc-r-pc 1 2 3 4 5 port1 a1-10pa-2.54dsa port1 a1-10pa-2.54dsa 1 2 3 4 5 6 7 8 9 10 c10 0.1u c10 0.1u test2 test2 r12 470 r12 470 test1 test1 u2 ak4118 u2 ak4118 ips0/rx4 1 nc 2 dif0/rx5 3 test2 4 dif1/rx6 5 vss1 6 dif2/rx7 7 ips1/iic 8 p/sn 9 xtl0 10 xtl1 11 tvdd 13 nc/gp1 14 tx0/gp2 15 tx1/gp3 16 bout/gp4 17 cout/gp5 18 uout/gp6 19 vout/gp7 20 dvdd 21 vss2 22 mcko1 23 bick 26 mcko2 27 daux 28 xto 29 xti 30 pdn 31 cm0/cdto/cad1 32 cm1/cdti/sda 33 ocks1/cclk/scl 34 ocks0/csn/cad0 35 int0 36 avdd 38 r 39 vcom 40 vss3 41 rx0 42 nc 43 rx1 44 test1 45 rx2 46 vss4 47 rx3 48 vin/gp0 12 lrck 24 sdto 25 int1 37 c12 0.1u c12 0.1u d1 hsu119 d1 hsu119 k a c17 0.1u c17 0.1u r4 51 r4 51 r9 (open) r9 (open) port2 torx141 port2 torx141 out 1 vcc 3 gnd 2 r2 (open) r2 (open)
a a b b c c d d e e e e d d c c b b a a ext-lrck ext-bick ext-mclk vcc vcc vcc vcc vcc title size document number rev date: sheet of external master clock divider 7 akd4440 a4 35 friday, may 08, 2009 title size document number rev date: sheet of external master clock divider 7 akd4440 a4 35 friday, may 08, 2009 title size document number rev date: sheet of external master clock divider 7 akd4440 a4 35 friday, may 08, 2009 x1 x3 x2 x3 x2 x4 x2 x1 x8 x1 x1 x3 x2 ext ext div clk bcfs lrfs open j2 bnc-r-pc j2 bnc-r-pc 1 2 3 4 5 jp13 (3x2) jp13 (3x2) 1 3 5 6 4 2 jp11 (3x2) jp11 (3x2) 1 3 5 6 4 2 u9a 74hc14 u9a 74hc14 1 2 14 7 u9c 74hc14 u9c 74hc14 5 6 u9f 74hc14 u9f 74hc14 13 12 u9b 74hc14 u9b 74hc14 3 4 u9e 74hc14 u9e 74hc14 11 10 r14 51 r14 51 jp10 (4x2) jp10 (4x2) 1 2 3 4 5 6 7 8 jp12 (2x1) jp12 (2x1) jp9 (3x2) jp9 (3x2) 1 3 5 6 4 2 u5b 74ac74 u5b 74ac74 d 12 q 9 clk 11 q 8 pr 10 cl 13 vcc 14 gnd 7 u7 74hc4040 u7 74hc4040 clk 10 rst 11 q1 9 q2 7 q3 6 q4 5 q5 3 q6 2 q7 4 q8 13 q9 12 q10 14 q11 15 q12 1 vcc 16 gnd 8 u5a 74ac74 u5a 74ac74 d 2 q 5 clk 3 q 6 pr 4 cl 1 vcc 14 gnd 7 u9d 74hc14 u9d 74hc14 9 8 u8 74ac163 u8 74ac163 a 3 qa 14 b 4 qb 13 c 5 qc 12 d 6 qd 11 rco 15 enp 7 ent 10 clk 2 load 9 clr 1 vcc 16 gnd 8
a a b b c c d d e e e e d d c c b b a a ak4440-rout1 ak4440-lout1 ak4440-rout2 ak4440-lout2 ak4440-rout3 ak4440-lout3 ak4440-rout4 ak4440-lout4 ak4440-tdm0b ak4440-dif0 ak4440-acks ak4440-dem0 ak4440-smute ak4440-i2c/dem1 ak4440-p/s vcc ak4440-acks ak4440-dif0 ak4440-smute vcc ak4440-dif0/cdti/sda ak4440-acks/cclk/scl ak4440-smute/cns/cad0 ak4440-p/s title size document number rev date: sheet of analog output 7 akd4440 a3 45 friday, may 08, 2009 title size document number rev date: sheet of analog output 7 akd4440 a3 45 friday, may 08, 2009 title size document number rev date: sheet of analog output 7 akd4440 a3 45 friday, may 08, 2009 rout1 lout1 rout2 lout2 rout3 lout3 rout4 lout4 dem0 smute acks p/s tdm0b dem1/i2c dif0 cclk/sci cdti/sda csn csn cdti cclk r24 470 r24 470 r28 100 r28 100 r23 10k r23 10k c27 3.3n c27 3.3n r16 (short) r16 (short) r35 (open) r35 (open) c25 3.3n c25 3.3n sw2 mode2 sw2 mode2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 j8 bnc-r-pc j8 bnc-r-pc 1 2 3 4 5 j5 bnc-r-pc j5 bnc-r-pc 1 2 3 4 5 + c28 (short) + c28 (short) r20 (open) r20 (open) r31 470 r31 470 c19 3.3n c19 3.3n r44 (open) r44 (open) r42 560 r42 560 r29 100 r29 100 + c30 (short) + c30 (short) r43 (short) r43 (short) r33 560 r33 560 r30 10k r30 10k r47 (open) r47 (open) c33 3.3n c33 3.3n r38 (open) r38 (open) r36 560 r36 560 + c18 (short) + c18 (short) r34 (short) r34 (short) + c26 (short) + c26 (short) j9 bnc-r-pc j9 bnc-r-pc 1 2 3 4 5 r37 (short) r37 (short) r15 560 r15 560 r32 100 r32 100 c21 3.3n c21 3.3n c23 3.3n c23 3.3n r26 10k r26 10k port3 up-i/f port3 up-i/f 1 2 3 4 5 6 7 8 9 10 j6 bnc-r-pc j6 bnc-r-pc 1 2 3 4 5 r41 (open) r41 (open) c29 3.3n c29 3.3n r18 560 r18 560 u10 74hct157 u10 74hct157 1a 2 1b 3 2a 5 2b 6 3a 11 3b 10 4a 14 4b 13 a/b 1 g 15 1y 4 2y 7 3y 9 4y 12 + c24 (short) + c24 (short) j7 bnc-r-pc j7 bnc-r-pc 1 2 3 4 5 j3 bnc-r-pc j3 bnc-r-pc 1 2 3 4 5 r17 (open) r17 (open) rp2 10k rp2 10k 1 2 3 4 5 6 7 8 9 r45 560 r45 560 r46 (short) r46 (short) j4 bnc-r-pc j4 bnc-r-pc 1 2 3 4 5 c31 3..3n c31 3..3n r27 470 r27 470 r19 (short) r19 (short) r39 560 r39 560 r25 (open) r25 (open) r21 560 r21 560 j10 bnc-r-pc j10 bnc-r-pc 1 2 3 4 5 + c22 (short) + c22 (short) r40 (short) r40 (short) + c32 (short) + c32 (short) r22 (short) r22 (short) + c20 (short) + c20 (short)
a a b b c c d d e e e e d d c c b b a a vddi vcci vddi vcci avdd avdd vdd vcc avdd vcc1 avdd1 title size document number rev date: sheet of power supply 7 akd4440 a4 55 friday, may 08, 2009 title size document number rev date: sheet of power supply 7 akd4440 a4 55 friday, may 08, 2009 title size document number rev date: sheet of power supply 7 akd4440 a4 55 friday, may 08, 2009 dgnd agnd for 74hc14 x 1, 74hct04 x 1, 74ac74 x 1, 74hc4040 x 1, 74ac163 x 1, 74hc14 x 1 vdd gnd avss1 dgnd avss1 avss2 avss2 avss1 t_45(black) avss1 t_45(black) 1 l3 (short) l3 (short) 1 2 r50 (short) r50 (short) avdd t_45(red) avdd t_45(red) 1 c36 0.1u c36 0.1u c42 0.1u c42 0.1u c41 0.1u c41 0.1u jp14 (2x1) jp14 (2x1) vcc t_45(red) vcc t_45(red) 1 jp16 (2x1) jp16 (2x1) c37 0.1u c37 0.1u l4 (short) l4 (short) 1 2 l2 (short) l2 (short) 1 2 c38 0.1u c38 0.1u + c43 47u + c43 47u + c34 47u + c34 47u dgnd t_45(black) dgnd t_45(black) 1 avss2 t_45(black) avss2 t_45(black) 1 c40 0.1u c40 0.1u + c35 47u + c35 47u c39 0.1u c39 0.1u jp15 (2x1) jp15 (2x1) r49 (short) r49 (short) vdd t_45(red) vdd t_45(red) 1 r48 (short) r48 (short)
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